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H
20 MBd High CMR Logic Gate Optocouplers Technical Data
HCPL-2400 HCPL-2430
Features
* High Speed: 40 MBd Typical Data Rate * High Common Mode Rejection: HCPL-2400: 10 kV/s at VCM = 300 V (Typical) * AC Performance Guaranteed over Temperature * High Speed AlGaAs Emitter * Compatible with TTL, STTL, LSTTL, and HCMOS Logic Families * Totem Pole and Tri State Output (No Pull Up Resistor Required) * Safety Approval UL Recognized - 2500 V rms for 1 minute per UL1577 VDE 0884 Approved with VIORM = 630 V peak (Option 060) for HCPL-2400 CSA Approved * High Power Supply Noise Immunity * MIL-STD-1772 Version Available (HCPL-5400/1 and HCPL-5430/1)
Applications
* Isolation of High Speed Logic Systems * Computer-Peripheral Interfaces * Switching Power Supplies * Isolated Bus Driver (Networking Applications) * Ground Loop Elimination * High Speed Disk Drive I/O * Digital Isolation for A/D, D/A Conversion * Pulse Transformer Replacement
Description
The HCPL-2400 and HCPL-2430 high speed optocouplers combine an 820 nm AlGaAs light emitting diode with a high speed photodetector. This combination results in very high data rate capability and low input current. The totem pole output (HCPL2430) or three state output (HCPL-2400) eliminates the need for a pull up resistor and allows for direct drive of data buses.
Functional Diagram
HCPL-2400 1 NC ANODE 2 CATHODE 3 4 NC VCC 8 7 VE 6 VO 5 ANODE 1 1 CATHODE 1 2 CATHODE 2 3 ANODE 2 4 HCPL-2430 8 VCC 7 VO1 6 VO2 5 GND
GND
TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ENABLE L L H H OUTPUT L H Z Z TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1-300
5965-3586E
The detector has optical receiver input stage with built-in Schmitt trigger to provide logic compatible waveforms, eliminating the need for additional waveshaping. The hysteresis provides differential mode noise immunity and minimizes the potential for output signal chatter.
The electrical and switching characteristics of the HCPL-2400 and HCPL-2430 are guaranteed over the temperature range of 0C to 70C. These optocouplers are compatible with TTL, STTL, LSTTL, and HCMOS logic
families. When Schottky type TTL devices (STTL) are used, a data rate performance of 20 MBd over temperature is guaranteed when using the application circuit of Figure 13. Typical data rates are 40 MBd.
Selection Guide
8-Pin DIP (300 Mil) Minimum CMR
Single Channel Package HCPL-2400
Dual Channel Package HCPL-2430
dV/dt (V/s) 1000 1000 500 500 500
VCM (V) 300 50 50 50 50
Minimum Input On Current (mA) 4 4 6 6 6
Maximum Propagation Delay (ns) 60 60 60 60 60
Hermetic Package
HCPL-540X* HCPL-543X* HCPL-643X*
*Technical data for the Hermetic HCPL-5400/01, HCPL-5430/31, and HCPL-6430/31 are on separate HP publications.
Ordering Information
Specify Part Number followed by Option Number (if desired). Example: HCPL-2400#XXX 060 = VDE 0884 VIORM = 630 V peak Option* 300 = Gull Wing Surface Mount Option 500 = Tape and Reel Packaging Option
*For HCPL-2400 only.
ICC
Schematic
1 IF1 + VF1 - 2 IO
8
VCC
ICC IE IO
7
VO1
8 7 6
VCC VE VO
ANODE
2 IF + - 3
VF CATHODE 5 3 - VF2 + 4 IF2 SHIELD TRUTH TABLE (POSITIVE LOGIC) LED OUTPUT ON L OFF H IO 6 VO2
GND
5
TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ENABLE L L H H OUTPUT L H Z Z
GND
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Package Outline Drawings
8-Pin DIP Package (HCPL-2400, HCPL-2430)
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
OPTION CODE* DATE CODE
HP XXXXZ YYWW RU 1 1.19 (0.047) MAX. 2 3 4
UL RECOGNITION
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN.
1.080 0.320 (0.043 0.013)
0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.
8-Pin DIP Package with Gull Wing Surface Mount Option 300 (HCPL-2400, HCPL-2430)
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040) 1.194 (0.047)
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
1
2
3
4
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 0.25 (0.025 0.010)
12 NOM.
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Solder Reflow Temperature Profile (Gull Wing Surface Mount Option 300 Parts)
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
1
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
Regulatory Information
The HCPL-24XX has been approved by the following organizations: VDE Approved according to VDE 0884/06.92 (Option 060 only).
UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324.
Insulation and Safety Related Specifications
Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(101) Value 7.1 Units mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. DIN IEC 112/VDE 0303 Part 1
L(102)
7.4
mm
0.08
mm
CTI
200
Volts
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
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VDE 0884 Insulation Related Characteristics (HCPL-2400 OPTION 060 ONLY)
Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 V rms for rated mains voltage 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure 12, Thermal Derating curve.) Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I-IV I-III 55/85/21 2 630 1181 Units
VIORM VPR
V peak V peak
VPR
945
V peak
VIOTM
6000
V peak
TS IS,INPUT PS,OUTPUT RS
175 230 600 109
C mA mW
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884) for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits in application.
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Absolute Maximum Ratings
(No derating required up to 70C) Parameter Storage Temperature Operating Temperature Average Forward Input Current Peak Forward Input Current Reverse Input Voltage Three State Enable Voltage (HCPL-2400 Only) Supply Voltage Average Output Collector Current Output Collector Voltage Output Voltage Output Collector Power Dissipation (Each Channel) Total Package Power Dissipation (Each Channel) Lead Solder Temperature (for Through Hole Devices) Reflow Temperature Profile (Option #300) Symbol TS TA IF(AVG) IFPK VR VE VCC IO VO VO PO PT -0.5 0 -25 -0.5 -0.5 Minimum -55 -40 Maximum 125 85 10 20 2 10 7 25 10 18 40 350 Units C C mA mA V V V mA V V mW mW 12 Note
260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section
Recommended Operating Conditions
Parameter Power Supply Voltage Forward Input Current (ON) Forward Input Voltage (OFF) Fan Out Enable Voltage (Low) HCPL-2400 Only) Enable Voltage (High) HCPL-2400 Only) Operating Temperature Symbol VCC IF(ON) VF(OFF) N VEL VEH TA Minimum 4.75 4 Maximum 5.25 8 0.8 5 0.8 VCC 70 Units V mA V TTL Loads V V C
0 2 0
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Electrical Specifications
0C TA 70C, 4.75 V VCC 5.25 V, 4 mA IF(ON) 8 mA, 0 V VF(OFF) 0.8 V. All typicals at TA = 25C, VCC = 5 V, IF(ON) = 6.0 mA, VF(OFF) = 0 V, except where noted. See Note 11.
Device Parameter Symbol HCPL- Min. Typ.* Max. Units Logic Low Output Voltage VOL 0.5 V Logic High Output Voltage Output Leakage Current Logic High Enable Current Logic Low Enable Voltage Logic High Enable Current Logic Low Enable Current Logic Low Supply Current VOH IOHH VEH VEL IEH IEL ICCL 2.4 2.7 100 2400 2400 2400 2400 2400 2430 2400 2430 High Impedance State Supply Current High Impedance State Output Current Logic Low Short Circuit Output Current Logic High Short Circuit Output Current Input Current Hysteresis Input Forward Voltage Input Reverse Breakdown Voltage Temperature Coefficient of Forward Voltage Input Capacitance ICCZ IOZL IOZH IOZH IOSL IOSH IHYS VF BVR VF TA CIN 0.25 1.1 1.0 3.0 2.0 -1.44 mV/C IF = 6 mA 4 52 -45 2400 2400 -0.28 19 34 17 32 22 2.0 0.8 20 100 -0.4 26 46 26 42 28 20 20 100 mA A A A mA mA mA 1.3 5.0 1.5 1.55 V TA = 25C IR = 10 A V A V V A mA mA Test Conditions Fig. IOL = 8.0 mA (5 TTL Loads) 1 IOH = -4.0 mA IOH = -0.4 mA VO = 5.25 V, VF = 0.8 V 2 Note
VE = 2.4 V VE = 5.25 V VE = 0.4 V VCC = 5.25 V, VE = 0 V, IO = Open VCC = 5.25 V, IO = Open VCC = 5.25 V, VE = 0 V, IO = Open VCC = 5.25 V, IO = Open VCC = 5.25 V, VE = 5.25 V VO = 0.4 V VO = 2.4 V VO = 5.25 V VO = VCC = 5.25 V, IF = 8 mA VCC = 5.25 V, IF = 0 mA, VO = GND VCC = 5 V TA = 25C 3 IF = 8 mA 4 2 2 VE = 2 V
Logic High Supply Current
ICCH
mA
20
pF
f = 1 MHz, VF = 0 V
*All typical values at TA = 25C and VCC = 5 V, unless otherwise noted.
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Switching Specifications
0C TA 70C, 4.75 V VCC 5.25 V, 4 mA IF(ON) 8 mA, 0 V VF(OFF) 0.8 V. All typicals at TA = 25C, VCC = 5 V, IF(ON) = 6.0 mA, VF(OFF) = 0 V, except where noted. See Note 11.
Parameter Propagation Delay Time to Logic Low Output Level Propagation Delay Time to Logic High Output Level Pulse Width Distortion Propagation Delay Skew Output Rise Time Output Fall Time Output Enable Time to Logic High Output Enable Time to Logic Low Output Disable Time from Logic High Output Disable Time from Logic Low Logic High Common Mode Transient Immunity Logic Low Common Mode Transient Immunity Power Supply Noise Immunity Symbol tPHL 15 tPLH 15 |tPHL-tPLH| 30 2 5 tPSK tr tf tPZH tPZL tPHZ tPLZ |CMH| 2400 2400 2400 2400 20 10 15 30 20 15 1000 10,000 33 Device HCPL- Min. Typ.* Max. 55 60 55 60 15 25 35 ns ns ns ns ns ns ns V/s VCM = 300 V, TA = 25C, IF = 0 mA VCM = 300 V, TA = 25C, IF = 4 mA VCC = 5.0 V, 48 Hz = FAC 50 MHz Per Notes & Text 15, 16 5 5 9, 10 9, 10 9, 10 9, 10 11 9 7 ns IF(ON) = 7 mA 5, 8 6 ns IF(ON) = 7 mA 5, 6, 7 1, 4, 5, 6 Units ns Test Conditions IF(ON) = 7 mA Figure Note 5, 6, 7 1, 4, 5, 6
|CML|
1000 10,000
V/s
11
9
PSNI
0.5
Vp-p
10
*All typical values at TA = 25C and VCC = 5 V, unless otherwise noted.
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Package Characteristics
Parameter Input-Output Momentary Withstand Voltage** Input-Output Resistance Input-Output Capacitance Input-Input Insulation Leakage Current Resistance (Input-Input) Capacitance (Input-Input) Sym. VISO Device Min. 2500 Typ.* Max. Units V rms Test Conditions RH 50%, t = 1 min., TA = 25C VI-O = 500 Vdc f = 1 MHz VI-O = 0 Vdc RH 45% t = 5 s, VI-I = 500 Vdc VI-I = 500 Vdc f = 1 MHz Fig. Note 3, 13
RI-O CI-O II-I 2430
1012 0.6 0.005
pF A
3
8
RI-I CI-I
2430 2430
1011 0.25
pF
8 8
*All typical values are at TA = 25C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publication number 5963-2203E. Notes: 1. Each channel. 2. Duration of output short circuit time not to exceed 10 ms. 3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 4. tPHL propagation delay is measured from the 50% level on the rising edge of the input current pulse to the 1.5 V level on the falling edge of the output pulse. The tPLH propagation delay is measured from the 50% level on the falling edge of the input current pulse to the 1.5 V level on the rising edge of the output pulse. 5. The typical data shown is indicative of what can be expected using the application circuit in Figure 13. 6. This specification simulates the worst case operating conditions of the HCPL-2400 over the recommended operating temperature and VCC range with the suggested application circuit of Figure 13. 7. Propagation delay skew is discussed later in this data sheet. 8. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. 9. Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V. Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 10. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and still remain in the desired logic state. For desired logic high state, VOH(MIN) > 2.0 V, and for desired logic low state, VOL(MAX) < 0.8 V. 11. Use of a 0.1 F bypass capacitor connected between pins 8 and 5 adjacent to the device is required. 12. Peak Forward Input Current pulse width < 50 s at 1 KHz maximum repetition rate. 13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for one second (leakage detection current limit, II-O 5 A). This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
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Figure 1. Typical Logic Low Output Voltage vs. Logic Low Output Current.
Figure 2. Typical Logic High Output Voltage vs. Logic High Output Current.
Figure 3. Typical Output Voltage vs. Input Forward Current.
Figure 4. Typical Diode Input Forward Current Characteristic.
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
Figure 6. Typical Propagation Delay vs. Ambient Temperature.
Figure 7. Typical Propagation Delay vs. Input Forward Current.
Figure 8. Typical Pulse Width Distortion vs. Ambient Temperature.
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Figure 9. Test Circuit for tPHZ, tPZH, tPLZ and tPZL.
Figure 10. Typical Enable Propagation Delay vs. Ambient Temperature.
HCPL-2400/11 1 NC IF B 2 3 4 NC GND VCC 8 7 6 5
VCC
OUTPUT POWER - PS, INPUT CURRENT - IS
0.1 F *
800 PS (mW) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 IS (mA)
+ VFF -
A
OUTPUT VO MONITORING NODE CL = 15 pF
VCM + - PULSE GENERATOR
TS - CASE TEMPERATURE - C
Figure 12. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884. Figure 11. Test Diagram for Common Mode Transient Immunity and Typical Waveforms.
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Applications
HCPL-2400 HCPL-2400 V
Figure 13. Recommended 20 MBd HCPL-2400/30 Interface Circuit.
Figure 14. Alternative HCPL-2400/30 Interface Circuit.
DATA
IF
50%
INPUTS CLOCK
VO
1.5 V
IF
50%
DATA OUTPUTS
t PSK
VO
1.5 V t PSK
CLOCK
t PSK
Figure 15. Illustration of Propagation Delay Skew - tPSK.
Figure 16. Parallel Data Transmission Example.
Figure 17. Modulation Code Selections.
Figure 18. Typical HCPL-2400/30 Output Schematic.
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Propagation Delay, PulseWidth Distortion and Propagation Delay Skew
Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 5). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will
determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 15, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 16 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signals are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of
the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPHZ. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-2400/30 optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges.
Application Circuit
A recommended LED drive circuit is shown in Figure 13. This circuit utilizes several techniques to minimize the total pulse-width distortion at the output of the optocoupler. By using two inverting TTL gates connected in series, the inherent pulse-width distortion of each gate cancels the distortion of the other gate. For best results, the two seriesconnected gates should be from the same package. The circuit in Figure 13 also uses techniques known as prebias and peaking to enhance the performance of the optocoupler LED. Prebias is a small forward voltage applied to the LED when the LED is off. This small prebias voltage partially charges the junction capacitance of the LED, allowing the LED to turn on more quickly. The speed of the LED is further increased by applying
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momentary current peaks to the LED during the turn-on and turnoff transitions of the drive current. These peak currents help to charge and discharge the capacitances of the LED more quickly, shortening the time required for the LED to turn on and off.
Switching performance of the HCPL-2400/30 optocouplers is not sensitive to the TTL logic family used in the recommended drive circuit. The typical and worst-case switching parameters given in the data sheet can be met using common 74LS TTL inverting gates or buffers. Use of faster TTL families will slightly reduce the overall propagation delays from the input of the drive circuit
to the output of the optocoupler, but will not necessarily result in lower pulse-width distortion or propagation delay skew. This reduction in overall propagation delay is due to shorter delays in the drive circuit, not to changes in the propagation delays of the optocoupler; optocoupler propagation delays are not affected by the speed of the logic used in the drive circuit.
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